UGN-01P: parametric linear-feedback shift register

Projects and Examples
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Cordial greetings everyone, just thought i’d share the patch-version of my UGN-01 module. Hope you have fun~

daisyPatch-UGN-01D.001
daisyPatch-UGN-01D.0011920×1080 389 KB

Description

high-playable parametric linear-feedback shift register.

The UGN-01P is a patch prototype of UGN-01 module. It is a unit generator for both organized and random control voltages and gates. It is operationally simple but contains extensive potential for expression.

UGN-01 exposes the inner workings of a linear-feedback shift register, providing parametric control to tap positions, clock rate, and seed to allow musical exploration and expression across the different time scales of music.

bit

Controls

Control Description Comment
Ctrl 1 - 4 CV Inputs Tap position. Ctrl as scaler, offsets when there is CV input.
Gate In 1 Ext Clock External clock input.
Gate In 2 Re/seed Seed LFSR with new value.
Encoder Menu Navigation Turn to navigate, press to edit.
Gate Out BIT OUT LFSR shift bit gate out.
CV Out 1 - 2 LFSR Register Outs CV Output of LFSR register value and its NOT respectively
Audio Out 1 - 4 Tap bit gate Output Bit state at n-th tap.
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Media

Tap Shift Lock

2 Likes
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Hey Jprecursor, I love your project idea, but I can’t seem to have access to a download link for it. Is there any other way to download than this “bit” button? it doesn’t seem to link me anywhere. Thanks!

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link fixed, marcugarcia. should be good to go now.

cheers,
jon

1 Like
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@jprecursor , I have a minor suggestion if you don’t mind. Using inverted value as second CV output feels a bit wasteful - it’s easy to invert signal using common analog utilities. You could probably utilize it for something more interesting. For example, XOR current register value with previous, output LFSR using different endianness or do something else not easily done outside the module.

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@antisvin thanks for the suggestion and feedback. I think the suggestions are great and will explore and experiment with them.

I may have described it wrongly using the term “inverse”, what happens at CV output 2 is putting each bit in the LFSR through a NOT operator.

Here’s a 4-bit example to illustrate this:

Output Binary Decimal
CV 1 1101 13
CV 2 0010 2

Cheers,
Jon

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Jon,

That bitwise invertion still means you’re outputting just pow(2, sizeof(LFSR)) - 1 - CV1. And the first value is a constant. So you’ll be getting something like this with 4 bit LFSR:

Binary CV1 Decimal CV1 Binary CV2 Decimal CV2
0000 0 1111 15
0001 1 1110 14
0010 2 1101 13
… … … …
1110 14 0001 1
1111 15 0000 0

The same value can also be obtained by inverting CV1 and adding voltage produced for value 15, so it’s linearly depending on CV1.