Daisy Patch Gate In Circuit Problem?

Hi,

I’m quite new to electronics, and using the Daisy Seed to develop some kind of “hardware prototyping framework” for my Eurorack modular needs. There is something I don’t understand well with the Daisy Patch Gate In schematic.

The Gate In circuit has a voltage divider, shows a 100k impendance to the outside world, and the other resistor is 1M. From what I understand, this would mean that the tension of the transistor base is VIN * 1M / (1M + 1k) ~ VIN.

A “normal” gate signal is +5V, but the electrical eurorack specifications say that the A-100 modules can take up to 12V.

Eurorack users could make mistakes by connecting for example an ADSR into a Gate. Furthermore, the popular Arturia Beat Step Pro delivers gates at +12V.

At the same time, the maximum rating of the MMBT3904 for the Emitter — Base Voltage is 6V.

Would using the Beat Step Pro with the Daisy Patch damage the Gate In over time? Or is there something I didn’t quite well understand in the circuit? Why not using a 100k or slightly lower in place of the 1M resistor?

And somehow same question if the user connects a LFO to the Gate In, so the Base — Emitter could see a reverse voltage of -5V. The datasheet puts a 1N916 diode for that on page 2, wouldn’t that be required as well to short the input to GND if a negative tension is applied?

Thanks for any information on that matter!

Raphael

Reading a bit more about transistors, it looks like I got it wrong:

  • Having a tension of 12V between the base and the emitter should be fine (but apart from the example in the datasheet, I don’t see how to verify that),
  • Having a reverse tension –5V (with a LFO for example), would be below the reverse breakdown voltage of the base-emitter junction (6V) and so this would be fine as well.

The only case would be if a malfunctioning module would send for example –12V to the gate, but this is very unlikely to happen. Still in that case, using a diode would prevent that problem.

Could someone confirm that?

If someone could send a link on how to ensure the tension between the base and emitter can be 12V would be really nice :slight_smile: Is it because the polarity for the Collector−Base Breakdown Voltage does not matter, and this would give 12V – 3.3V = 8.7V which is way smaller than 60V?

Thanks!

Raphael

Given this is a npn transistor, Vbe could never get that high, because with a positive Vbe the transistor will start to conduct and then Vbe is limited. Have a look at figure 19 in the datasheet. At room temperature it will be between 0.6 and about 1.1 Volts at max dependng on the current.